1. Field of the Invention
The present invention relates to a semiconductor integrated circuit device, and more particularly, to a semiconductor integrated circuit device including a boosting circuit boosting an internal potential level.
2. Description of the Background Art
FIG. 18 is a schematic block diagram showing the configuration of a high voltage generating circuit within a conventional semiconductor integrated circuit device.
Referring to FIG. 18, a high voltage generating circuit 10 includes, a main charge pump circuit 11, a sub charge pump circuit 12, a main charge pump limiting circuit 13, and a sub charge pump limiting circuit 14.
Sub charge pump circuit 12 boosts an external power-supply potential ext.Vcc, and outputs the boosted potential to main charge pump circuit 11 as a supply potential VWDP.
Main charge pump circuit 11 receives supply potential VWDP, and further boosts supply potential VWDP and outputs it as a boosted potential VPP. Boosted potential VPP is supplied to each internal circuit within the semiconductor integrated circuit device.
Sub charge pump limiting circuit 14 includes a differential amplifying circuit, determines whether or not supply potential VWDP has reached a predetermined potential level, and outputs the result of the determination as a determination signal CPW0. Similarly, main charge pump limiting circuit 13 determines whether or not boosted potential VPP has reached a predetermined potential level, and outputs the result of the determination as a determination signal CPWW. It is noted that, when boosted potential VPP has not yet reached a predetermined potential level, determination signal CPWW is output as a logic high or xe2x80x9cHxe2x80x9d level. On the other hand, when boosted potential VPP has already reached a predetermined potential level, determination signal CPWW is output as a logic low or xe2x80x9cLxe2x80x9d level.
Main charge pump circuit 11 receives an internal clock signal int.CLK2 output from a clock generating circuit 15, to perform boosting operation. Moreover, sub charge pump circuit 12 receives an internal clock signal int.CLK1 output from clock generating circuit 15 to perform boosting operation.
Clock generating circuit 15 receives an externally-input serial clock signal SC, and outputs internal clock signals int.CLK1 and int.CLK2.
Now, when a write voltage is generated in high voltage generating circuit 10 shown in FIG. 18, main charge pump circuit 11 uses supply potential VWDP output from sub charge pump circuit 12 to boost the potential level of boosted potential VPP.
At that moment, in order to increase a writing speed, a boosting speed of boosted potential VPP must be increased.
Furthermore, the potential of boosted potential VPP is raised as time passes, while sub charge pump circuit 12 continues operating even after boosted potential VPP attains to a potential level sufficient to perform the writing operation. This has caused a problem of large power consumption.
An object of the present invention is to provide a semiconductor integrated circuit device including a boosting circuit in which an internal potential can be boosted at a high speed while power consumption can be reduced.
According to one aspect of the present invention, a semiconductor integrated circuit device includes a booster boosting an internal potential level. The booster includes a first boosting circuit boosting the internal potential level, and a second boosting circuit boosting a level of a supply potential supplied to the first boosting circuit. The second boosting circuit includes a plurality of boosting stages for boosting the supply potential level, and a boost control circuit changing the number of the boosting stages to be operated.
By increasing the number of boosting stages to be operated within the second boosting circuit, the first boosting circuit can attain a higher boosting speed of the internal potential level.
Moreover, by reducing the number of boosting stages to be operated within the second boosting circuit, power consumption can be reduced.
Preferably, the boost control circuit changes the number of boosting stages to be operated after a predetermined time has elapsed from activation of the first boosting circuit.
Preferably, the boost control circuit includes a timer circuit, and the timer circuit performs time measurement after reception of an activation signal of the booster.
Thus, the number of boosting stages to be operated within the second circuit is reduced depending on boosting time of the internal potential level, resulting in reduction of power consumption.
Preferably, the semiconductor integrated circuit device further includes a determination circuit determining whether or not an internal potential level boosted by the booster is at a predetermined potential level. The boost control circuit changes the number of boosting stages to be operated, in response to a determination result of the determination circuit.
Thus, by reducing the number of boosting stages to be operated within the second boosting circuit when the internal potential level reaches a predetermined potential level, power consumption can be reduced.
According to another aspect of the present invention, a semiconductor integrated circuit device includes a booster boosting an internal potential level, a determination circuit determining whether or not an internal potential level boosted by the booster has reached a predetermined potential level, and a clock generating circuit receiving an external signal and generating an internal clock signal. The clock generating circuit stops generation of the internal clock signal when the determination circuit determines that the internal potential level has reached a predetermined potential level.
This allows reduction of power consumption.
Preferably, the semiconductor integrated circuit device includes a plurality of boosters, and a plurality of determination circuits provided for each of the boosters. The clock generating circuit stops generation of the internal clock signal when all of the determination circuits determine that a potential level boosted by each of the boosters is at a predetermined potential level.
Thus, the clock generating circuit continues operating until all of the potential levels boosted by the plurality of boosters reach a predetermined potential level.
Preferably, the clock generating circuit receives an activation signal generated from an external signal to start operating, and invalidates the activation signal when all of the determination circuits determine that the potential level boosted by each of the boosters is at a predetermined potential level.
Thus, the activation signal itself is invalidated, to stop the operation of the clock generating circuit.
Preferably, the clock generating circuit includes a plurality of clock frequency-dividing circuits each changing a frequency of the clock signal. Each of the clock frequency-dividing circuits invalidates the activation signal when all of the potential levels boosted by the plurality of boosters each receiving the clock signal of a same frequency reach a predetermined potential level.
This allows clock signals to be stopped for each group of boosters receiving clock signals of the same frequency.
As described above, in the high voltage generating circuit, the number of boosting stages operated within the sub charge pump is changed. As a result, the boosting speed for the boosted potential output from the main charge pump can be increased.
Moreover, when the boosted potential approaches a predetermined potential, the number of boosting stages operated within the sub charge pump is reduced. As a result, power consumption can be reduced.
Furthermore, when the boosted potential reaches a predetermined potential, the operation of the clock generating circuit is stopped. As a result, power consumption can further be reduced.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.